Magnetic random access memory (MRAM) is a non-volatile memory that uses magnetism rather than electrical power to store data. FIG. 1 shows a schematic diagram of a portion 10 of an MRAM array, which includes a plurality of memory cells 12–19. Each memory cell 12–19 includes a magnetoresistive (MR) stack 20–27 and a transistor 30–37. The transistors 30–33 are coupled to each other via a word line (WL1) 40, and transistors 34–37 are coupled to each other via a word line (WL2) 41, where the word lines 40, 41 form the gate electrode for the transistors 30–37. The transistors 30–33 are also coupled to each other via a program line (PL1) 42, and transistors 34–37 are coupled via a program line (PL2) 43, where the program lines 42, 43 serve as virtual ground lines. Similarly, the MR stacks 20 and 24 are coupled to each other by bit line (BL1) 45, MR stacks 21 and 25 are coupled to each other by bit line (BL2) 46, MR stacks 22 and 26 are coupled to each other by bit line (BL3) 47, and MR stacks 23 and 27 are coupled to each other by bit line (BL4) 48. The bit lines 45–48 are typically somewhat perpendicular to the word lines 40, 41 and the program lines 42, 43.
Each of the MR stacks 20–27 is a multi-layer magnetoresistive structure, such as a magnetic tunneling junction (MTJ) or a giant magnetoresistive (GMR) structure. FIG. 2 shows an example of a typical MTJ structure 50. The MTJ structure 50 includes four basic layers: a free layer 52, a spacer 54 which serves as a tunneling barrier, a pinned layer 56, and a pinning layer 58. The free layer 52 and the pinned layer 56 are constructed of ferromagnetic material, for example cobalt-iron or nickel-cobalt-iron. The pinning layer 58 is constructed of antiferromagnetic material, for example platinum manganese. Magnetostatic coupling between the pinned layer 56 and the pinning layer 58 causes the pinned layer 56 to have a fixed magnetic moment. The free layer 52, on the other hand, has a magnetic moment that, by application of a magnetic field, can be switched between a first orientation, which is parallel to the magnetic moment of the pinned layer 56, and a second orientation, which is antiparallel to the magnetic moment of the pinned layer 56.
The spacer 54 interposes the pinned layer 56 and the free layer 52. The spacer 54 is composed of insulating material, for example aluminum oxide, magnesium oxide, or tantalum oxide. The spacer 54 is formed thin enough to allow the transfer (tunneling) of spin-aligned electrons when the magnetic moments of the free layer 52 and the pinned layer 56 are parallel. On the other hand, when the magnetic moments of the free layer 52 and the pinned layer 56 are antiparallel, the probability of electrons tunneling through the spacer 54 is reduced. This phenomenon is commonly referred to as spin-dependent tunneling (SDT).
As shown in FIG. 3, the electrical resistance through the MTJ 50 (e.g., through layers 52–58) increases as the moments of the pinned and free layers become more antiparallel and decreases as they become more parallel. In an MRAM memory cell, the electrical resistance of the MTJ 50 can therefore be switched between first and second resistance values representing first and second logic states. For example, a high resistance value can represent a logic state “1” and a low resistance value can represent a logic state “0”. The logic states thus stored in the memory cells can be read by passing a sense current through the MR stack and sensing the resistance. For example, referring back to FIG. 1, the logic state of memory cell 12 can be read by passing a sense current through bit line (BL1) 45, activating transistor 30 via word line (WL1) 40, and sensing the current passing to program line (PL1) 42.
FIG. 4 shows a layout of the portion 10 of the MRAM array, where MR stacks 20–27 and word lines 40, 41 are shown in broken lines, and transistors 30–37 are omitted for the sake of clarity. During a write operation, electrical current flows through a program line 42, 43 and a bit line 45–48 that intersect at the target memory cell 12–19. For example, in order to write to memory cell 13, a current is passed through program line (PL1) 42 and a current is passed through bit line (BL2) 46. The magnitude of these currents is selected such that, ideally, the resulting magnetic fields are not strong enough on their own to affect the memory state of the MR stacks 20–23 and 25, but the combination of the two magnetic fields (at MR stack 21) is sufficient for switching the memory state (e.g., switching the magnetic moment of the free layer 52) of the MR stack 21.
However, in practice, the states of neighboring MR stacks 20, 22, and 25 can be affected by the magnetic field at the intersection of bit line (BL2) 46 and program line (PL1) 42, resulting in an unstable memory device. In order to avoid this problem, the memory array 10 is designed such that neighboring cells are separated by distance R. The distance R is selected such that neighboring memory cells are positioned outside the influence of intersecting magnetic fields. Typically, the magnitude of a magnetic field felt by a neighboring MR stack is inversely proportional to the square of the distance R between the neighboring MR stacks. As a consequence, memory cell density (i.e., number of memory cells per unit area) is limited due to the distance requirements necessary to ensure a stable memory device.